


第1頁:
                                        74HC4040;  74HCT4040
                                        12-stage binary ripple counter
                                        Rev. 03 — 14 September 2005                      Product data sheet
            1.   General description
                                    The 74HC4040; 74HCT4040 are high-speed Si-gate CMOS devices and are pin
                                    compatible with the HEF4040B series. They are specified in compliance with JEDEC
                                    standard no.7A.
                                    The 74HC4040; 74HCT4040 are 12-stage binary ripple counters with a clock input (CP),
                                    an overriding asynchronous master reset input (MR) and twelve parallel outputs (Q0 to
                                    Q11). The counter advances on the HIGH-to-LOW transition ofCP.
                                    A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the
                                    state ofCP.
                                    Each counter stage is a static toggle flip-flop.
            2.   Features
                                    n  Multiple package options
                                    n  Complies with JEDEC standard no. 7A
                                    n  ESD protection:
                                         u  HBMJESD22-A114-C exceeds 2000V
                                         u  MMJESD22-A115-A exceeds 200V
                                    n  Specified from-  40(cid:176) Cto+85(cid:176) C and from-  40(cid:176) Cto+125(cid:176) C
            3.   Applications
                                    n  Frequency dividing circuits
                                    n  Time delay circuits
                                    n  Control counters
            4.   Quick reference data
                                    Table 1:   Quick reference data
                                    GND=0V;Tamb=25(cid:176) C;t=t=6r  f   ns.
                                     Symbol     Parameter              Conditions                   Min   Typ   Max  Unit
                                     Type 74HC4040
                                     tPHL, tPLH    propagation delay
                                                    CP to Q0              CL =15 pF; VCC =5V         -      14    -      ns
                                                    Qn to Qn+1            CL =15 pF; VCC =5V         -      8     -      ns

![第1頁圖片](http://192.168.15.113:48763/uploadImg/view/YanBun_74HC4040_page_1.png)



第2頁:
                                                                                74HC4040;  74HCT4040
            Philips Semiconductors
                                                                                                  12-stage binary ripple counter
                                    Table 1:   Quick reference data …continued
                                    GND=0V;Tamb=25(cid:176) C;t=t=6r  f   ns.
                                     Symbol     Parameter              Conditions                   Min   Typ   Max  Unit
                                     fmax         maximum operating      CL =15 pF; VCC =5V         -      90    -      MHz
                                                  frequency
                                     Ci           input capacitance                                       -      3.5   -      pF
                                     CPD         power dissipation        VI =GND to VCC              -      20    -      pF
                                                  capacitance
                                     Type 74HCT4040
                                     tPHL, tPLH    propagation delay
                                                    CP to Q0              CL =15 pF; VCC =5V         -      16    -      ns
                                                    Qn to Qn+1            CL =15 pF; VCC =5V         -      8     -      ns
                                     fmax         maximum operating      CL =15 pF; VCC =5V         -      79    -      MHz
                                                  frequency
                                     Ci           input capacitance                                       -      3.5   -      pF
                                     CPD         power dissipation        VI =GND to VCC -  1.5V      -      20    -      pF
                                                  capacitance
                                    [1]  CPD is used to determine the dynamic power dissipation (PD inm  W):
                                         PD =CPD ·  VCC2·  fi +(cid:229)  (CL ·  VCC2·  fo) where:
                                         fi =input frequency in MHz;
                                         fo =output frequency in MHz;
                                         (cid:229)  (CL ·  VCC2·  fo)=sum of outputs;
                                         CL =output load capacitance in pF;
                                         VCC =supply voltage in V.
            5.   Ordering information
            Table 2:   Ordering information
            Type number   Package
                             Temperature range    Name       Description                                       Version
            74HC4040N    -  40(cid:176) C to +125(cid:176) C      DIP16       plastic dual in-line package; 16 leads (300 mil);     SOT38-1
                                                                   long body
            74HC4040D    -  40(cid:176) C to +125(cid:176) C      SO16       plastic small outline package; 16 leads; body       SOT109-1
                                                                   width3.9 mm
            74HC4040DB   -  40(cid:176) C to +125(cid:176) C      SSOP16    plasticshrinksmalloutlinepackage;16leads;body  SOT338-1
                                                                   width 5.3 mm
            74HC4040PW   -  40(cid:176) C to +125(cid:176) C      TSSOP16   plastic thin shrink small outline package; 16 leads;  SOT403-1
                                                                   body width 4.4 mm
            74HC4040BQ   -  40(cid:176) C to +125(cid:176) C      DHVQFN16  plastic dual in-line compatible thermal enhanced    SOT763-1
                                                                   verythinquadflatpackage;noleads;16terminals;
                                                                   body2.5·  3.5·  0.85 mm
            74HCT4040N   -  40(cid:176) C to +125(cid:176) C      DIP16       plastic dual in-line package; 16 leads (300 mil);     SOT38-1
                                                                   long body
            74HCT4040D   -  40(cid:176) C to +125(cid:176) C      SO16       plastic small outline package; 16 leads; body       SOT109-1
                                                                   width3.9 mm
            74HC_HCT4040_3                                                                            ©KoninklijkePhilipsElectronicsN.V.2005.Allrightsreserved.
            Product data sheet                             Rev. 03 — 14 September 2005                                        2 of 24

![第2頁圖片](http://192.168.15.113:48763/uploadImg/view/YanBun_74HC4040_page_2.png)



第3頁:
                                                                                74HC4040;  74HCT4040
            Philips Semiconductors
                                                                                                  12-stage binary ripple counter
            Table 2:   Ordering information …continued
            Type number   Package
                             Temperature range    Name       Description                                       Version
            74HCT4040DB  -  40(cid:176) C to +125(cid:176) C      SSOP16    plasticshrinksmalloutlinepackage;16leads;body  SOT338-1
                                                                   width 5.3 mm
            74HCT4040PW  -  40(cid:176) C to +125(cid:176) C      TSSOP16   plastic thin shrink small outline package; 16 leads;  SOT403-1
                                                                   body width 4.4 mm
            74HCT4040BQ  -  40(cid:176) C to +125(cid:176) C      DHVQFN16  plastic dual in-line compatible thermal enhanced    SOT763-1
                                                                   verythinquadflatpackage;noleads;16terminals;
                                                                   body2.5·  3.5·  0.85 mm
            6.   Functional diagram
                                                       CP   10  T
                                                            11                12-STAGE COUNTER
                                                      MR      CD
                                                                  9  7  6  5  3  2  4  13  12  14  15  1
                                                                Q0  Q1  Q2  Q3  Q4  Q5  Q6  Q7  Q8  Q9  Q10Q11
                                                                                                          001aad589
                                      Fig 1.  Functional diagram
                                                                                                          CTR12
                                                              Q0   9                             10   +        0   9
                                                              Q1   7                             11   CT = 0        7
                                                              Q2   6                                                6
                                                   10   CP   Q3   5                                                5
                                                              Q4   3                                                3
                                                              Q5   2                                       CT      2
                                                              Q6   4                                                4
                                                   11   MR   Q7   13                                               13
                                                              Q8   12                                               12
                                                              Q9   14                                               14
                                                             Q10   15                                               15
                                                             Q11   1                                           11  1
                                                              001aad585                                         001aad586
                                      Fig 2.  Logic symbol                          Fig 3.  IEC logic symbol
            74HC_HCT4040_3                                                                            ©KoninklijkePhilipsElectronicsN.V.2005.Allrightsreserved.
            Product data sheet                             Rev. 03 — 14 September 2005                                        3 of 24

![第3頁圖片](http://192.168.15.113:48763/uploadImg/view/YanBun_74HC4040_page_3.png)



第4頁:
                                                                                74HC4040;  74HCT4040
            Philips Semiconductors
                                                                                                  12-stage binary ripple counter
                                                    FF Q         FF Q         FF Q         FF Q         FF Q         FF Q
                                       CP         T  1          T  2          T  3          T  4          T  5          T  6
                                                       Q            Q            Q            Q            Q            Q
                                                    RD           RD           RD           RD           RD           RD
                                      MR
                                                          Q0           Q1           Q2           Q3           Q4           Q5
                                                    FF Q         FF Q         FF Q         FF Q         FF Q         FF Q
                                                  T  7          T  8          T  9          T  10         T  11         T  12
                                                       Q            Q            Q            Q            Q            Q
                                                    RD           RD           RD           RD           RD           RD
                                                          Q6           Q7           Q8           Q9          Q10          Q11
                                                                                                                           001aad588
                                      Fig 4.  Logic diagram
            7.   Pinning information
                              7.1  Pinning
                                                                                           terminal 1        11Q  CCV
                                                                                           index area
                                          Q11  1                       16  VCC                            1  61
                                           Q5  2                       15  Q10                   Q5  2             15  Q10
                                           Q4  3                       14  Q9                    Q4  3             14  Q9
                                           Q6  4                       13  Q7                    Q6  4             13  Q7
                                                          4040                                             4040
                                           Q3  5                       12  Q8                    Q3  5             12  Q8
                                           Q2  6                       11  MR                    Q2  6   GND(1)   11  MR
                                           Q1  7                       10  CP                    Q1  7             10  CP
                                          GND  8                       9  Q0                             8  9
                                                                001aad583                                   DNG  0Q
                                                                                                                      001aad584
                                                                                                      Transparent top view
                                                                                         (1)  The substrate is attached to this pad
                                                                                              usingconductivedieattachmaterial.It
                                                                                              can not be used as supply pin or input
                                      Fig 5.  Pin configuration DIP16, SO16,        Fig 6.  Pin configuration DHVQFN16
                                             SSOP16 and TSSOP16
            74HC_HCT4040_3                                                                            ©KoninklijkePhilipsElectronicsN.V.2005.Allrightsreserved.
            Product data sheet                             Rev. 03 — 14 September 2005                                        4 of 24

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第5頁:
                                                                                74HC4040;  74HCT4040
            Philips Semiconductors
                                                                                                  12-stage binary ripple counter
                              7.2  Pin description
                                    Table 3:   Pin description
                                     Symbol          Pin        Description
                                     Q11              1          output 11
                                     Q5               2          output 5
                                     Q4               3          output 4
                                     Q6               4          output 6
                                     Q3               5          output 3
                                     Q2               6          output 2
                                     Q1               7          output 1
                                     GND             8          ground (0 V)
                                     Q0               9          output 0
                                     CP               10         clock input (HIGH-to-LOW, edge-triggered)
                                     MR              11         master reset input (active HIGH)
                                     Q8               12         output 8
                                     Q7               13         output 7
                                     Q9               14         output 9
                                     Q10              15         output 10
                                     VCC              16         positive supply voltage
            8.   Functional description
                              8.1  Function table
                                    Table 4:   Function table
                                     Input                                                          Output
                                     CP                             MR                            Q0 to Q11
                                     ›                                L                              no change
                                     fl                                L                              count
                                     X                              H                              L
                                    [1]  H=HIGH voltage level;
                                         L=LOW voltage level;
                                         X=don’t care;
                                         ›  =LOW-to-HIGH clock transition;
                                         fl  =HIGH-to-LOW clock transition.
            74HC_HCT4040_3                                                                            ©KoninklijkePhilipsElectronicsN.V.2005.Allrightsreserved.
            Product data sheet                             Rev. 03 — 14 September 2005                                        5 of 24

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第6頁:
                                                                                74HC4040;  74HCT4040
            Philips Semiconductors
                                                                                                  12-stage binary ripple counter
                              8.2  Timing diagram
                                                              1  2   4   8   16  32  64  128  256  512  1024  2048  4096
                                              CP input
                                             MR input
                                                  Q0
                                                  Q1
                                                  Q2
                                                  Q3
                                                  Q4
                                                  Q5
                                                  Q6
                                                  Q7
                                                  Q8
                                                  Q9
                                                 Q10
                                                 Q11
                                                                                                                   001aad587
                                      Fig 7.  Timing diagram
            9.   Limiting values
            Table 5:   Limiting values
            InaccordancewiththeAbsoluteMaximumRatingSystem(IEC60134).VoltagesarereferencedtoGND(ground=0V).
            Symbol    Parameter                            Conditions                                Min    Max    Unit
            VCC        supply voltage                                                                    -  0.5    +7      V
            IIK          input diode current                    VI <-  0.5V or VI > VCC +0.5V             -       –  20    mA
            IOK         output diode current                   VI <-  0.5V or VI > VCC +0.5 V              -       –  20    mA
            IO          output source or sink current           -  0.5V < VO < VCC +0.5 V                  -       –  25    mA
            ICC         quiescent supply current                                                           -       –  50    mA
            IGND       ground current                                                                    -       –  50    mA
            Tstg        storage temperature                                                               -  65    +150   (cid:176) C
            Ptot        power dissipation                      Tamb =-  40(cid:176) C to +125(cid:176) C               [1]
                           DIP16 package                                                                 -       750    mW
                           SO16, SSOP16, TSSOP16 and                                                 -       500    mW
                           DHVQFN16 packages
            [1]  For DIP16 packages: above 70(cid:176) C, Ptot derates linearly with 12mW/K.
                For SO16, SSOP16, TSSOP16 and DHVQFN16 packages, above 70(cid:176) C, Ptot derates linearly with 8mW/K.
            74HC_HCT4040_3                                                                            ©KoninklijkePhilipsElectronicsN.V.2005.Allrightsreserved.
            Product data sheet                             Rev. 03 — 14 September 2005                                        6 of 24

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第7頁:
                                                                                74HC4040;  74HCT4040
            Philips Semiconductors
                                                                                                  12-stage binary ripple counter
            10.  Recommended operating conditions
            Table 6:   Recommended operating conditions
            Symbol     Parameter                         Conditions                            Min    Typ    Max   Unit
            type 74HC4040
            VCC         supply voltage                                                              2.0    5.0    6.0    V
            VI           input voltage                                                                0      -       VCC    V
            VO          output voltage                                                              0      -       VCC    V
            Tamb         ambient temperature               seeSection11 and12 per device       -  40    -       +125  (cid:176) C
            t,r  tf          input rise and fall times             except for Schmitt-trigger inputs
                                                                VCC = 2.0V                          -       -       1000  ns
                                                                VCC = 4.5V                          -       6.0    500    ns
                                                                VCC = 6.0V                          -       -       400    ns
            type 74HCT4040
            VCC         supply voltage                                                              4.5    5.0    5.5    V
            VI           input voltage                                                                0      -       VCC    V
            VO          output voltage                                                              0      -       VCC    V
            Tamb         ambient temperature               seeSection11 and12 per device       -  40    -       +125  (cid:176) C
            t,r  tf          input rise and fall times             except for Schmitt-trigger inputs
                                                                VCC = 2.0V                          -       -       -       ns
                                                                VCC = 4.5V                          -       6.0    500    ns
                                                                VCC = 6.0V                          -       -       -       ns
            11.  Static characteristics
            Table 7:   Static characteristics for 74HC4040
            VoltagesarereferencedtoGND(ground=0V).
            Symbol     Parameter                    Conditions                           Min      Typ      Max     Unit
            Tamb = 25(cid:176) C
            VIH         HIGH-level input voltage       VCC = 2.0V                           1.5       1.2       -         V
                                                        VCC = 4.5V                           3.15     2.4       -         V
                                                        VCC = 6.0V                           4.2       3.2       -         V
            VIL          LOW-level input voltage       VCC = 2.0V                           -         0.8       0.5       V
                                                        VCC = 4.5V                           -         2.1       1.35     V
                                                        VCC = 6.0V                           -         2.8       1.8       V
            VOH         HIGH-level output voltage     VI = VIH or VIL
                                                          IO =-  20m  A; VCC = 2.0V            1.9       2.0       -         V
                                                          IO =-  20m  A; VCC = 4.5V            4.4       4.5       -         V
                                                          IO =-  20m  A; VCC = 6.0V            5.9       6.0       -         V
                                                          IO =-  4.0mA; VCC =4.5V           3.98     4.32     -         V
                                                          IO =-  5.2mA; VCC =6.0V           5.48     5.81     -         V
            74HC_HCT4040_3                                                                            ©KoninklijkePhilipsElectronicsN.V.2005.Allrightsreserved.
            Product data sheet                             Rev. 03 — 14 September 2005                                        7 of 24

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第8頁:
                                                                                74HC4040;  74HCT4040
            Philips Semiconductors
                                                                                                  12-stage binary ripple counter
            Table 7:   Static characteristics for 74HC4040 …continued
            VoltagesarereferencedtoGND(ground=0V).
            Symbol     Parameter                    Conditions                           Min      Typ      Max     Unit
            VOL         LOW-level output voltage      VI = VIH or VIL
                                                          IO = 20m  A; VCC = 2.0V              -         0         0.1       V
                                                          IO = 20m  A; VCC = 4.5V              -         0         0.1       V
                                                          IO = 20m  A; VCC = 6.0V              -         0         0.1       V
                                                          IO = 4.0mA; VCC = 4.5V            -         0.15     0.26     V
                                                          IO = 5.2mA; VCC = 6.0V            -         0.16     0.26     V
            ILl           input leakage current          VI = VCC orGND; VCC = 6.0V          -         -         0.1       m  A
            ICC          quiescent supply current      VI = VCC orGND; IO = 0 A;             -         -         8.0       m  A
                                                        VCC = 6.0V
            CI          input capacitance                                                    -         3.5       -         pF
            Tamb =-  40(cid:176) C to +85(cid:176) C
            VIH         HIGH-level input voltage       VCC = 2.0V                           1.5       -         -         V
                                                        VCC = 4.5V                           3.15     -         -         V
                                                        VCC = 6.0V                           4.2       -         -         V
            VIL          LOW-level input voltage       VCC = 2.0V                           -         -         0.5       V
                                                        VCC = 4.5V                           -         -         1.35     V
                                                        VCC = 6.0V                           -         -         1.8       V
            VOH         HIGH-level output voltage     VI = VIH or VIL
                                                          IO =-  20m  A; VCC = 2.0V            1.9       -         -         V
                                                          IO =-  20m  A; VCC = 4.5V            4.4       -         -         V
                                                          IO =-  20m  A; VCC = 6.0V            5.9       -         -         V
                                                          IO =-  4.0mA; VCC = 4.5V           3.84     -         -         V
                                                          IO =-  5.2mA; VCC = 6.0V;           5.34     -         -         V
            VOL         LOW-level output voltage      VI = VIH or VIL
                                                          IO = 20m  A; VCC = 2.0V              -         -         0.1       V
                                                          IO = 20m  A; VCC = 4.5V              -         -         0.1       V
                                                          IO = 20m  A; VCC = 6.0V              -         -         0.1       V
                                                          IO = 4.0mA; VCC = 4.5V            -         -         0.33     V
                                                          IO = 5.2mA; VCC = 6.0V            -         -         0.33     V
            ILl           input leakage current          VI = VCC orGND; VCC = 6.0V          -         -         1.0       m  A
            ICC          quiescent supply current      VI = VCC orGND; IO = 0 A;             -         -         80.0     m  A
                                                        VCC = 6.0V
            Tamb =-  40(cid:176) C to +125(cid:176) C
            VIH         HIGH-level input voltage       VCC = 2.0V                           1.5       -         -         V
                                                        VCC = 4.5V                           3.15     -         -         V
                                                        VCC = 6.0V                           4.2       -         -         V
            VIL          LOW-level input voltage       VCC = 2.0V                           -         -         0.5       V
                                                        VCC = 4.5V                           -         -         1.35     V
                                                        VCC = 6.0V                           -         -         1.8       V
            74HC_HCT4040_3                                                                            ©KoninklijkePhilipsElectronicsN.V.2005.Allrightsreserved.
            Product data sheet                             Rev. 03 — 14 September 2005                                        8 of 24

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第9頁:
                                                                                74HC4040;  74HCT4040
            Philips Semiconductors
                                                                                                  12-stage binary ripple counter
            Table 7:   Static characteristics for 74HC4040 …continued
            VoltagesarereferencedtoGND(ground=0V).
            Symbol     Parameter                    Conditions                           Min      Typ      Max     Unit
            VOH         HIGH-level output voltage     VI = VIH or VIL
                                                          IO =-  20m  A; VCC = 2.0V            1.9       -         -         V
                                                          IO =-  20m  A; VCC = 4.5V            4.4       -         -         V
                                                          IO =-  20m  A; VCC = 6.0V            5.9       -         -         V
                                                          IO =-  4.0mA; VCC = 4.5V           3.7       -         -         V
                                                          IO =-  5.2mA; VCC = 6.0V;           5.2       -         -         V
            VOL         LOW-level output voltage      VI = VIH or VIL
                                                          IO = 20m  A; VCC = 2.0V              -         -         0.1       V
                                                          IO = 20m  A; VCC = 4.5V              -         -         0.1       V
                                                          IO = 20m  A; VCC = 6.0V              -         -         0.1       V
                                                          IO = 4.0mA; VCC = 4.5V            -         -         0.4       V
                                                          IO = 5.2mA; VCC = 6.0V            -         -         0.4       V
            ILl           input leakage current          VI = VCC orGND; VCC =6.0V          -         -         1.0       m  A
            ICC          quiescent supply current      VI = VCC orGND; IO = 0 A;             -         -         160.0    m  A
                                                        VCC =6.0V
            Table 8:   Static characteristics for 74HCT4040
            VoltagesarereferencedtoGND(ground=0V).
            Symbol     Parameter                  Conditions                           Min      Typ      Max      Unit
            Tamb = 25(cid:176) C
            VIH          HIGH-level input voltage     VCC = 4.5V to 5.5V                   2.0       1.6       -         V
            VIL          LOW-level input voltage      VCC = 4.5V to 5.5V                   -         1.2       0.8       V
            VOH         HIGH-level output voltage    VI = VIH or VIL
                                                         IO =-  20m  A; VCC = 4.5V            4.4       4.5       -         V
                                                         IO =-  4.0mA; VCC = 4.5V           3.98      4.32      -         V
            VOL         LOW-level output voltage    VI = VIH or VIL
                                                         IO = 20m  A; VCC = 4.5V             -         0         0.1       V
                                                         IO = 4.0mA; VCC = 4.5V            -         0.15      0.26      V
            ILl           input leakage current        VI = VCC orGND; VCC = 5.5V          -         -         0.1       m  A
            ICC          quiescent supply current     VI = VCC orGND; IO = 0A;             -         -         8.0       m  A
                                                       VCC = 5.5V
            D  ICC         additional quiescent supply  VI = VCC -  2.1V; VCC = 4.5V
                          current                      to 5.5V; IO = 0 A
                                                         CP                                 -         85        306      m  A
                                                         MR                                 -         110      396      m  A
            CI           input capacitance                                                   -         3.5       -         pF
            Tamb =-  40(cid:176) C to +85(cid:176) C
            VIH          HIGH-level input voltage     VCC = 4.5V to 5.5V                   2.0       -         -         V
            VIL          LOW-level input voltage      VCC = 4.5V to 5.5V                   -         -         0.8       V
            74HC_HCT4040_3                                                                            ©KoninklijkePhilipsElectronicsN.V.2005.Allrightsreserved.
            Product data sheet                             Rev. 03 — 14 September 2005                                        9 of 24

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第10頁:
                                                                                74HC4040;  74HCT4040
            Philips Semiconductors
                                                                                                  12-stage binary ripple counter
            Table 8:   Static characteristics for 74HCT4040 …continued
            VoltagesarereferencedtoGND(ground=0V).
            Symbol     Parameter                  Conditions                           Min      Typ      Max      Unit
            VOH         HIGH-level output voltage    VI = VIH or VIL
                                                         IO =-  20m  A; VCC = 4.5V            4.4       -         -         V
                                                         IO =-  4.0mA; VCC = 4.5V           3.84      -         -         V
            VOL         LOW-level output voltage    VI = VIH or VIL
                                                         IO = 20m  A; VCC = 4.5V             -         -         0.1       V
                                                         IO = 4.0mA; VCC = 4.5V            -         -         0.33      V
            ILl           input leakage current        VI = VCC orGND; VCC = 5.5V          -         -         1.0       m  A
            ICC          quiescent supply current     VI = VCC orGND; IO = 0 A;             -         -         80.0      m  A
                                                       VCC = 5.5V
            D  ICC         additional quiescent supply  VI = VCC -  2.1V; VCC = 4.5V
                          current                      to 5.5V; IO = 0 A
                                                         CP                                 -         -         383      m  A
                                                         MR                                 -         -         495      m  A
            Tamb =-  40(cid:176) C to +125(cid:176) C
            VIH          HIGH-level input voltage     VCC = 4.5V to 5.5V                   2.0       -         -         V
            VIL          LOW-level input voltage      VCC = 4.5V to 5.5V                   -         -         0.8       V
            VOH         HIGH-level output voltage    VI = VIH or VIL
                                                         IO =-  20m  A; VCC = 4.5V            4.4       -         -         V
                                                         IO =-  4.0mA; VCC = 4.5V           3.7       -         -         V
            VOL         LOW-level output voltage    VI = VIH or VIL
                                                         IO = 20m  A; VCC = 4.5V             -         -         0.1       V
                                                         IO = 4.0mA; VCC = 4.5V            -         -         0.4       V
            ILl           input leakage current        VI = VCC orGND; VCC = 5.5V          -         -         1.0       m  A
            ICC          quiescent supply current     VI = VCC orGND; IO = 0A;             -         -         160.0     m  A
                                                       VCC = 5.5V
            D  ICC         additional quiescent supply  VI = VCC -  2.1V; VCC = 4.5V
                          current                      to 5.5V; IO =0A
                                                         CP                                 -         -         417      m  A
                                                         MR                                 -         -         539      m  A
            74HC_HCT4040_3                                                                            ©KoninklijkePhilipsElectronicsN.V.2005.Allrightsreserved.
            Product data sheet                             Rev. 03 — 14 September 2005                                       10 of 24

![第10頁圖片](http://192.168.15.113:48763/uploadImg/view/YanBun_74HC4040_page_10.png)



第11頁:
                                                                                74HC4040;  74HCT4040
            Philips Semiconductors
                                                                                                  12-stage binary ripple counter
            12.  Dynamic characteristics
            Table 9:   Dynamic characteristics for type 74HC4040
            GND=0V;tr=tf=6ns.FortestcircuitseeFigure9.
            Symbol     Parameter                         Conditions                          Min    Typ    Max    Unit
            Tamb = 25(cid:176) C
            tPHL, tPLH    propagation delayCP to Q0         seeFigure8
                                                                VCC =2.0 V; CL =50pF            -       47      150    ns
                                                                VCC =4.5 V; CL =50pF            -       17      30      ns
                                                                VCC =5.0V; CL =15pF            -       14      -       ns
                                                                VCC =6.0V; CL =50pF            -       14      26      ns
                          propagation delay Qn to Qn+1      seeFigure8
                                                                VCC =2.0V; CL =50pF            -       28      100    ns
                                                                VCC =4.5V; CL =50pF            -       10      20      ns
                                                                VCC =5.0V; CL =15pF            -       8       -       ns
                                                                VCC =6.0 V; CL =50pF            -       8       17      ns
            tPHL         propagation delay MR to Qn        seeFigure8
                                                                VCC =2.0V; CL =50pF             -       61      185    ns
                                                                VCC = 4.5V; CL =50pF            -       22      37      ns
                                                                VCC = 6.0V; CL =50pF            -       18      31      ns
            tTHL, tTLH     output transition time               seeFigure8
                                                                VCC = 2.0V; CL =50pF            -       19      75      ns
                                                                VCC = 4.5V; CL =50pF            -       7       15      ns
                                                                VCC = 6.0V; CL =50pF            -       6       13      ns
            tW           clock pulse width HIGH or LOW     seeFigure8
                                                                VCC = 2.0V; CL =50pF            80      14      -       ns
                                                                VCC = 4.5V; CL =50pF            16      5       -       ns
                                                                VCC = 6.0V; CL =50pF            14      4       -       ns
                          master reset pulse width; HIGH     seeFigure8
                                                                VCC = 2.0V; CL =50pF            80      22      -       ns
                                                                VCC = 4.5V; CL =50pF            16      8       -       ns
                                                                VCC = 6.0V; CL =50pF            14      6       -       ns
            trec          recovery time MR toCP            seeFigure8
                                                                VCC = 2.0V; CL =50pF            50      8       -       ns
                                                                VCC = 4.5V; CL =50pF            10      3       -       ns
                                                                VCC = 6.0V; CL =50pF            9       2       -       ns
            fmax          maximum operating frequency      seeFigure8
                                                                VCC = 2.0V; CL =50pF            6.0     27      -       MHz
                                                                VCC = 4.5V; CL =50pF            30      82      -       MHz
                                                                VCC =5.0V; CL =15 pF            -       90      -       MHz
                                                                VCC = 6.0V; CL =50pF            35      98      -       MHz
            CPD         power dissipation capacitance                                            -       20      -       pF
            74HC_HCT4040_3                                                                            ©KoninklijkePhilipsElectronicsN.V.2005.Allrightsreserved.
            Product data sheet                             Rev. 03 — 14 September 2005                                       11 of 24

![第11頁圖片](http://192.168.15.113:48763/uploadImg/view/YanBun_74HC4040_page_11.png)



第12頁:
                                                                                74HC4040;  74HCT4040
            Philips Semiconductors
                                                                                                  12-stage binary ripple counter
            Table 9:   Dynamic characteristics for type 74HC4040 …continued
            GND=0V;tr=tf=6ns.FortestcircuitseeFigure9.
            Symbol     Parameter                         Conditions                          Min    Typ    Max    Unit
            Tamb =-  40(cid:176) C to +85(cid:176) C
            tPHL, tPLH    propagation delayCP to Q0         seeFigure8
                                                                VCC = 2.0V; CL =50pF            -       -       190    ns
                                                                VCC = 4.5V; CL =50pF            -       -       38      ns
                                                                VCC = 6.0V; CL =50pF            -       -       33      ns
                          propagation delay Qn to Qn+1      seeFigure8
                                                                VCC = 2.0V; CL =50pF            -       -       125    ns
                                                                VCC = 4.5V; CL =50pF            -       -       25      ns
                                                                VCC = 6.0V; CL =50pF            -       -       21      ns
            tPHL         propagation delay MR to Qn        seeFigure8
                                                                VCC = 2.0V; CL =50pF            -       -       230    ns
                                                                VCC = 4.5V; CL =50pF            -       -       46      ns
                                                                VCC = 6.0V; CL =50pF            -       -       39      ns
            tTHL, tTLH     output transition time               seeFigure8
                                                                VCC = 2.0V; CL =50pF            -       -       95      ns
                                                                VCC = 4.5V; CL =50pF            -       -       19      ns
                                                                VCC = 6.0V; CL =50pF            -       -       16      ns
            tW           clock pulse width HIGH or LOW     seeFigure8
                                                                VCC = 2.0V; CL =50pF            100    -       -       ns
                                                                VCC = 4.5V; CL =50pF            20      -       -       ns
                                                                VCC = 6.0V; CL =50pF            17      -       -       ns
                          master reset pulse width; HIGH     seeFigure8
                                                                VCC = 2.0V; CL =50pF            100    -       -       ns
                                                                VCC = 4.5V; CL =50pF            20      -       -       ns
                                                                VCC = 6.0V; CL =50pF            17      -       -       ns
            trec          recovery time MR toCP            seeFigure8
                                                                VCC = 2.0V; CL =50pF            65      -       -       ns
                                                                VCC = 4.5V; CL =50pF            13      -       -       ns
                                                                VCC = 6.0V; CL =50pF            11      -       -       ns
            fmax          maximum operating frequency      seeFigure8
                                                                VCC = 2.0V; CL =50pF            4.8     -       -       MHz
                                                                VCC = 4.5V; CL =50pF            24      -       -       MHz
                                                                VCC = 6.0V; CL =50pF            28      -       -       MHz
            74HC_HCT4040_3                                                                            ©KoninklijkePhilipsElectronicsN.V.2005.Allrightsreserved.
            Product data sheet                             Rev. 03 — 14 September 2005                                       12 of 24

![第12頁圖片](http://192.168.15.113:48763/uploadImg/view/YanBun_74HC4040_page_12.png)



第13頁:
                                                                                74HC4040;  74HCT4040
            Philips Semiconductors
                                                                                                  12-stage binary ripple counter
            Table 9:   Dynamic characteristics for type 74HC4040 …continued
            GND=0V;tr=tf=6ns.FortestcircuitseeFigure9.
            Symbol     Parameter                         Conditions                          Min    Typ    Max    Unit
            Tamb =-  40(cid:176) C to +125(cid:176) C
            tPHL, tPLH    propagation delayCP to Q0         seeFigure8
                                                                VCC = 2.0V; CL =50pF            -       -       225    ns
                                                                VCC = 4.5V; CL =50pF            -       -       45      ns
                                                                VCC = 6.0V; CL =50pF            -       -       38      ns
                          propagation delay Qn to Qn+1      seeFigure8
                                                                VCC = 2.0V; CL =50pF            -       -       150    ns
                                                                VCC = 4.5V; CL =50pF            -       -       30      ns
                                                                VCC = 6.0V; CL =50pF            -       -       26      ns
            tPHL         propagation delay MR to Qn        seeFigure8
                                                                VCC = 2.0V; CL =50pF            -       -       280    ns
                                                                VCC = 4.5V; CL =50pF            -       -       56      ns
                                                                VCC = 6.0V; CL =50pF            -       -       48      ns
            tTHL, tTLH     output transition time               seeFigure8
                                                                VCC = 2.0V; CL =50pF            -       -       110    ns
                                                                VCC = 4.5V; CL =50pF            -       -       22      ns
                                                                VCC = 6.0V; CL =50pF            -       -       19      ns
            tW           clock pulse width HIGH or LOW     seeFigure8
                                                                VCC = 2.0V; CL =50pF            120    -       -       ns
                                                                VCC = 4.5V; CL =50pF            24      -       -       ns
                                                                VCC = 6.0V; CL =50pF            20      -       -       ns
                          master reset pulse width; HIGH     seeFigure8
                                                                VCC = 2.0V; CL =50pF            120    -       -       ns
                                                                VCC = 4.5V; CL =50pF            24      -       -       ns
                                                                VCC = 6.0V; CL =50pF            20      -       -       ns
            trec          recovery time MR toCP            seeFigure8
                                                                VCC = 2.0V; CL =50pF            75      -       -       ns
                                                                VCC = 4.5V; CL =50pF            15      -       -       ns
                                                                VCC = 6.0 V; CL =50pF            13      -       -       ns
            fmax          maximum operating frequency      seeFigure8
                                                                VCC = 2.0V; CL =50pF            4.0     -       -       MHz
                                                                VCC = 4.5V; CL =50pF            20      -       -       MHz
                                                                VCC = 6.0V; CL =50pF            24      -       -       MHz
            [1]  CPD is used to determine the dynamic power dissipation (PD inm  W):
                PD =CPD ·  VCC2·  fi +(cid:229)  (CL ·  VCC2·  fo) where:
                fi =input frequency in MHz;
                fo =output frequency in MHz;
                (cid:229)  (CL ·  VCC2·  fo)=sum of outputs;
                CL =output load capacitance in pF;
                VCC =supply voltage in V.
            74HC_HCT4040_3                                                                            ©KoninklijkePhilipsElectronicsN.V.2005.Allrightsreserved.
            Product data sheet                             Rev. 03 — 14 September 2005                                       13 of 24

![第13頁圖片](http://192.168.15.113:48763/uploadImg/view/YanBun_74HC4040_page_13.png)



第14頁:
                                                                                74HC4040;  74HCT4040
            Philips Semiconductors
                                                                                                  12-stage binary ripple counter
            Table 10:  Dynamic characteristics for type 74HCT4040
            GND=0V;tr=tf=6ns.FortestcircuitseeFigure9.
            Symbol     Parameter                       Conditions                        Min     Typ     Max     Unit
            Tamb = 25(cid:176) C
            tPHL, tPLH     propagation delayCP to Q0       seeFigure8
                                                              VCC = 4.5V; CL =50pF          -        19      40      ns
                                                              VCC =5.0V; CL =15 pF          -        16      -        ns
                          propagation delay Qn to Qn+1    seeFigure8
                                                              VCC = 4.5V; CL =50pF          -        10      20      ns
                                                              VCC =5.0V; CL =15 pF          -        8        -        ns
            tPHL          propagation delay MR to Qn      VCC = 4.5 V; CL =50pF;           -        23      45      ns
                                                            seeFigure8;
            tTHL, tTLH     output transition time             VCC = 4.5 V; CL =50pF;           -        7        15      ns
                                                            seeFigure8;
            tW           clock pulse width HIGH or LOW   VCC = 4.5 V; CL =50pF;           16      7        -        ns
                                                            seeFigure8;
                          master reset pulse width; HIGH   VCC = 4.5 V; CL =50pF;           16      6        -        ns
                                                            seeFigure8;
            trec          recovery time MR toCP          VCC = 4.5 V; CL =50pF;           10      2        -        ns
                                                            seeFigure8;
            fmax          maximum operating frequency    seeFigure8
                                                              VCC = 4.5 V; CL =50pF          30      72      -        MHz
                                                              VCC =5.0V; CL =15 pF          -        79      -        MHz
            CPD         power dissipation capacitance                                     [1]  -        20      -        pF
                          per package
            Tamb =-  40(cid:176) C to +85(cid:176) C
            tPHL, tPLH     propagation delayCP to Q0       VCC = 4.5 V; CL =50pF;           -        -        50      ns
                                                            seeFigure8;
                          propagation delay Qn to Qn+1    VCC = 4.5 V; CL =50pF;           -        -        25      ns
                                                            seeFigure8;
            tPHL          propagation delay MR to Qn      VCC = 4.5 V; CL =50pF;           -        -        56      ns
                                                            seeFigure8;
            tTHL, tTLH     output transition time             VCC = 4.5 V; CL =50pF;           -        -        19      ns
                                                            seeFigure8;
            tW           clock pulse width HIGH or LOW   VCC = 4.5 V; CL =50pF;           20      -        -        ns
                                                            seeFigure8;
                          master reset pulse width; HIGH   VCC = 4.5 V; CL =50pF;           20      -        -        ns
                                                            seeFigure8;
            trec          recovery time MR toCP          VCC = 4.5 V; CL =50pF;           13      -        -        ns
                                                            seeFigure8;
            fmax          maximum operating frequency    VCC = 4.5 V; CL =50pF;           24      -        -        MHz
                                                            seeFigure8;
            Tamb =-  40(cid:176) C to +125(cid:176) C
            tPHL, tPLH     propagation delayCP to Q0       VCC = 4.5 V; CL =50pF;           -        -        60      ns
                                                            seeFigure8;
                          propagation delay Qn to Qn+1    VCC = 4.5 V; CL =50pF;           -        -        30      ns
                                                            seeFigure8
            74HC_HCT4040_3                                                                            ©KoninklijkePhilipsElectronicsN.V.2005.Allrightsreserved.
            Product data sheet                             Rev. 03 — 14 September 2005                                       14 of 24

![第14頁圖片](http://192.168.15.113:48763/uploadImg/view/YanBun_74HC4040_page_14.png)



第15頁:
                                                                                74HC4040;  74HCT4040
            Philips Semiconductors
                                                                                                  12-stage binary ripple counter
            Table 10:  Dynamic characteristics for type 74HCT4040 …continued
            GND=0V;tr=tf=6ns.FortestcircuitseeFigure9.
            Symbol     Parameter                       Conditions                        Min     Typ     Max     Unit
            tPHL          propagation delay MR to Qn      VCC = 4.5 V; CL =50pF;           -        -        68      ns
                                                            seeFigure8
            tTHL, tTLH     output transition time             VCC = 4.5 V; CL =50pF;           -        -        22      ns
                                                            seeFigure8
            tW           clock pulse width HIGH or LOW   VCC = 4.5 V; CL =50pF;           24      -        -        ns
                                                            seeFigure8
                          master reset pulse width; HIGH   VCC = 4.5 V; CL =50pF;           24      -        -        ns
                                                            seeFigure8
            trec          recovery time MR toCP          VCC = 4.5 V; CL =50pF;           15      -        -        ns
                                                            seeFigure8
            fmax          maximum operating frequency    VCC = 4.5 V; CL =50pF;           20      -        -        MHz
                                                            seeFigure8
            [1]  CPD is used to determine the dynamic power dissipation (PD inm  W):
                PD =CPD ·  VCC2·  fi +(cid:229)  (CL ·  VCC2·  fo) where:
                fi =input frequency in MHz;
                fo =output frequency in MHz;
                (cid:229)  (CL ·  VCC2·  fo)=sum of outputs;
                CL =output load capacitance in pF;
                VCC =supply voltage in V.
            13.  Waveforms
                                                              VI
                                                      MR input        VM
                                                                         tW              1/fmax
                                                                                     trem
                                                              VI
                                                      CP input                                        VM
                                                                                               tW
                                                              tPHL                     tPLH                tPHL
                                                      Q0 or Qn                                           VM
                                                      output
                                                                                       tTLH                tTHL
                                                                                                           001aad590
                                             74HC4040: VM =50 %; VI =GND to VCC.
                                             74HCT4040: VM =1.3 V; VI =GND to 3V.
                                      Fig 8.  Clock(CP)tooutput(Qn)propagationdelays,clockpulsewidth,outputtransition
                                             times, maximum clock pulse frequency, master reset (MR) pulse width, master
                                             reset to output (Qn) propagation delays and master reset to clock (CP) removal
                                             time.
            74HC_HCT4040_3                                                                            ©KoninklijkePhilipsElectronicsN.V.2005.Allrightsreserved.
            Product data sheet                             Rev. 03 — 14 September 2005                                       15 of 24

![第15頁圖片](http://192.168.15.113:48763/uploadImg/view/YanBun_74HC4040_page_15.png)



第16頁:
                                                                                74HC4040;  74HCT4040
            Philips Semiconductors
                                                                                                  12-stage binary ripple counter
                                                                                       VCC
                                                                 PULSE      VI               VO
                                                              GENERATOR             DUT
                                                                                   RT               CL
                                                                                                      mna101
                                             Definitions for test circuit:
                                             CL = load capacitance including jig and probe capacitance (SeeSection12 for the value).
                                             RT = termination resistance should be equal to output impedance ZO of the pulse generator.
                                      Fig 9.  Test circuit
            74HC_HCT4040_3                                                                            ©KoninklijkePhilipsElectronicsN.V.2005.Allrightsreserved.
            Product data sheet                             Rev. 03 — 14 September 2005                                       16 of 24

![第16頁圖片](http://192.168.15.113:48763/uploadImg/view/YanBun_74HC4040_page_16.png)



第17頁:
                                                                                74HC4040;  74HCT4040
            Philips Semiconductors
                                                                                                  12-stage binary ripple counter
            14.  Package outline
              DIP16: plastic dual in-line package; 16 leads (300 mil); long body                                       SOT38-1
                                                       D                                                  ME
                        enalp
                        gnitaes
                                                                                      A2  A
                                                                                  A1
                           L
                                                                                                    c
                               Z                e                                w M
                                                                           b1
                                                                                                          (e1)
                                                                b
                                 16                                        9                             MH
                                       pin 1 index
                                                                                      E
                                  1                                        8
                                                            0          5          10 mm
                                                                      scale
                DIMENSIONS (inch dimensions are derived from the original mm dimensions)
                  UNIT   mA    mAn1   mA2     b     b1     c     D(1)   E(1)    e     e1     L     ME    MH     w     Z(1)
                           ax.    i  .    ax.                                                                              max.
                   mm    4.7    0.51    3.7    1.40   0.53   0.32   21.8   6.48   2.54   7.62    3.9    8.25    9.5   0.254   2.2
                                               1.14   0.38   0.23   21.4   6.20                 3.4    7.80    8.3
                  inches   0.19   0.02   0.15   0.055  0.021  0.013   0.86   0.26    0.1    0.3    0.15   0.32   0.37   0.01   0.087
                                              0.045  0.015  0.009   0.84   0.24                 0.13   0.31   0.33
                Note
                1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
                     OUTLINE                              REFERENCES                             EUROPEAN
                     VERSION                                                                      PROJECTION     ISSUE DATE
                                       IEC           JEDEC          JEITA
                     SOT38-1         050G09         MO-001        SC-503-16                                        99-12-27
                                                                                                                    03-02-13
            Fig 10. Package outline SOT38-1 (DIP16)
            74HC_HCT4040_3                                                                            ©KoninklijkePhilipsElectronicsN.V.2005.Allrightsreserved.
            Product data sheet                             Rev. 03 — 14 September 2005                                       17 of 24

![第17頁圖片](http://192.168.15.113:48763/uploadImg/view/YanBun_74HC4040_page_17.png)



第18頁:
                                                                                74HC4040;  74HCT4040
            Philips Semiconductors
                                                                                                  12-stage binary ripple counter
              SO16: plastic small outline package; 16 leads; body width 3.9 mm                                    SOT109-1
                                                  D                                           E           A
                                                                                                                   X
                                                                              c
                                y                                                             HE                  v M  A
                              Z
                            16                                         9
                                                                                                       Q
                                                                                  A2                     (A )    A
                                                                                     A1                    3
                              pin 1 index
                                                                                                               q
                                                                                                     Lp
                             1                                         8                            L
                                             e                       bp    w M                detail X
                                                             0         2.5        5 mm
                                                                      scale
                DIMENSIONS (inch dimensions are derived from the original mm dimensions)
                  UNIT   A    A1   A2   A3   bp    c   D(1)  E(1)   e    HE    L    Lp    Q    v    w    y    Z(1)   q
                        max.
                  mm   1.75  0.25  1.45  0.25  0.49  0.25  10.0   4.0   1.27   6.2  1.05   1.0   0.7  0.25  0.25   0.1   0.7
                              0.10  1.25        0.36  0.19   9.8   3.8         5.8         0.4   0.6                    0.3    8o
                              0.010  0.057       0.019  0.0100  0.39  0.16       0.244       0.039  0.028                   0.028   0o
                 inches  0.069  0.004  0.049  0.01  0.014  0.0075  0.38  0.15  0.05  0.228  0.041  0.016  0.020  0.01  0.01  0.004  0.012
                Note
                1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
                     OUTLINE                              REFERENCES                             EUROPEAN
                     VERSION                                                                      PROJECTION     ISSUE DATE
                                       IEC           JEDEC          JEITA
                     SOT109-1         076E07          MS-012                                                         99-12-27
                                                                                                                    03-02-19
            Fig 11. Package outline SOT109-1 (SO16)
            74HC_HCT4040_3                                                                            ©KoninklijkePhilipsElectronicsN.V.2005.Allrightsreserved.
            Product data sheet                             Rev. 03 — 14 September 2005                                       18 of 24

![第18頁圖片](http://192.168.15.113:48763/uploadImg/view/YanBun_74HC4040_page_18.png)



第19頁:
                                                                                74HC4040;  74HCT4040
            Philips Semiconductors
                                                                                                  12-stage binary ripple counter
              SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm                          SOT338-1
                                             D                                           E              A
                                                                                                                X
                                                                      c
                                   y                                                     HE                     v M  A
                                  Z
                                 16                      9
                                                                                                   Q
                                                                              A2                     (A )    A
                                                                                 A1                    3
                                         pin 1 index
                                                                                                            q
                                                                                                 Lp
                                                                                                L
                                  1                      8                                  detail X
                                                       bp     w M
                                        e
                                                             0         2.5         5 mm
                                                                      scale
                DIMENSIONS (mm are the original dimensions)
                  UNIT  mA    A    A    A    bp    c   D(1)  E(1)   e    H     L    Lp    Q    v    w    y    Z(1)   q
                         ax.    1     2     3                                  E
                  mm    2   00..201  11..860  0.25  00..328  00..200   66..4   55..4   0.65   77..9   1.25  10..063   00..9   0.2   0.13   0.1   10..050   0o8
                                5    5          5    9    0    2          6           3    7                      5    o
                Note
                1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
                     OUTLINE                              REFERENCES                             EUROPEAN
                     VERSION                                                                      PROJECTION     ISSUE DATE
                                       IEC           JEDEC          JEITA
                     SOT338-1                        MO-150                                                        99-12-27
                                                                                                                    03-02-19
            Fig 12. Package outline SOT338-1 (SSOP16)
            74HC_HCT4040_3                                                                            ©KoninklijkePhilipsElectronicsN.V.2005.Allrightsreserved.
            Product data sheet                             Rev. 03 — 14 September 2005                                       19 of 24

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第20頁:
                                                                                74HC4040;  74HCT4040
            Philips Semiconductors
                                                                                                  12-stage binary ripple counter
              TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm                    SOT403-1
                                               D                                          E            A    X
                                                                         c
                                      y                                                   HE                   v M  A
                                         Z
                                   16                      9
                                                                                                      Q
                                                                             A2                         (A3)    A
                                          pin 1 index                             A1
                                                                                                              q
                                                                                                  Lp
                                                                                                L
                                    1                      8
                                                                w                           detail X
                                                         bp      M
                                             e
                                                             0         2.5         5 mm
                                                                      scale
                DIMENSIONS (mm are the original dimensions)
                  UNIT  mA    A1   A2   A3   bp    c   D(1)  E(2)   e    HE    L    Lp    Q    v    w    y    Z(1)   q
                         ax.
                  mm   1.1   00..105  00..985  0.25  00..310   00..2   54..1   44..5   0.65   66..6    1   00..755   00..4   0.2  0.13   0.1   00..400   0o8
                                5    0          9    1    9    3          2           0    3                      6    o
                Notes
                1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
                2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
                     OUTLINE                              REFERENCES                             EUROPEAN
                     VERSION                                                                      PROJECTION     ISSUE DATE
                                       IEC           JEDEC          JEITA
                     SOT403-1                        MO-153                                                         99-12-27
                                                                                                                    03-02-18
            Fig 13. Package outline SOT403-1 (TSSOP16)
            74HC_HCT4040_3                                                                            ©KoninklijkePhilipsElectronicsN.V.2005.Allrightsreserved.
            Product data sheet                             Rev. 03 — 14 September 2005                                       20 of 24

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第21頁:
                                                                                74HC4040;  74HCT4040
            Philips Semiconductors
                                                                                                  12-stage binary ripple counter
              DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
              16 terminals; body 2.5 x 3.5 x 0.85 mm                                                                 SOT763-1
                                                  D                   B  A
                                                                                            A
                                                                                              A1
                                                                          E                                          c
                      terminal 1                                                                           detail X
                      index area
                        terminal 1                 e1                                                            C
                        index area
                                       e                  b             v  M  C  A  B        y1 C                  y
                                   2                            7      w M  C
                           L
                              1                                      8
                           Eh                                           e
                             16                                      9
                                    15                        10
                                                 Dh
                                                                                                              X
                                             0                        2.5                        5 mm
                                                                      scale
                DIMENSIONS (mm are the original dimensions)
                 UNIT  A(1)   A1         c   D(1)        E(1)         e                          y
                       max.        b               Dh        Eh         e1    L    v    w         y1
                  mm   1   0.05  0.30  0.2   3.6  2.15  2.6  1.15  0.5   2.5   0.5   0.1  0.05  0.05  0.1
                             0.00  0.18        3.4  1.85  2.4  0.85              0.3
                Note
                1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
                     OUTLINE                              REFERENCES                             EUROPEAN
                     VERSION                                                                      PROJECTION     ISSUE DATE
                                       IEC           JEDEC          JEITA
                     SOT763-1          - - -           MO-241           - - -                                           02-10-17
                                                                                                                     03-01-27
            Fig 14. Package outline SOT763-1 (DHVQFN16)
            74HC_HCT4040_3                                                                            ©KoninklijkePhilipsElectronicsN.V.2005.Allrightsreserved.
            Product data sheet                             Rev. 03 — 14 September 2005                                       21 of 24

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第22頁:
                                                                                74HC4040;  74HCT4040
            Philips Semiconductors
                                                                                                  12-stage binary ripple counter
            15.  Revision history
            Table 11:  Revision history
            Document ID            Release date          Data sheet       Change    Doc.        Supersedes
                                                              status            notice     number
            74HC_HCT4040_3       20050914             Product data      -           -            74HC_HCT4040_CNV_2
                                                              sheet
            Modifications:              •  Theformatofthisdatasheethasbeenredesignedtocomplywiththenewpresentationand
                                           information standard of Philips Semiconductors
                                        •  Referencetofamilyspecificationsisreplacedbytheactualinformation:Section5“Ordering
                                           information”,Section 7 “Pinning information”,Section 9 “Limiting values”,Section 10
                                           “Recommended operating conditions”,Section 11 “Static characteristics”,Figure 9 “Test
                                           circuit”
                                        •  Section 14 “Package outline” (DHVQFN16) added
            74HC_HCT4040_CNV_2  19901231             Product           -           -            -
                                                              specification
            74HC_HCT4040_3                                                                            ©KoninklijkePhilipsElectronicsN.V.2005.Allrightsreserved.
            Product data sheet                             Rev. 03 — 14 September 2005                                       22 of 24

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第23頁:
                                                                                74HC4040;  74HCT4040
            Philips Semiconductors
                                                                                                  12-stage binary ripple counter
            16.  Data sheet status
            Level  Data sheet status[1]  Product status[2][3]  Definition
            I     Objective data       Development        This data sheet contains data from the objective specification for product development. Philips
                                                       Semiconductors reserves the right to change the specification in any manner without notice.
            II     Preliminary data     Qualification        Thisdatasheetcontainsdatafromthepreliminaryspecification.Supplementarydatawillbepublished
                                                       atalaterdate.PhilipsSemiconductorsreservestherighttochangethespecificationwithoutnotice,in
                                                       order to improve the design and supply the best possible product.
            III    Product data        Production          This data sheet contains data from the product specification. Philips Semiconductors reserves the
                                                       righttomakechangesatanytimeinordertoimprovethedesign,manufacturingandsupply.Relevant
                                                       changes will be communicated via a Customer Product/Process Change Notification (CPCN).
            [1]  Please consult the most recently issued data sheet before initiating or completing a design.
            [2]  The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
                URLhttp://www.semiconductors.philips.com.
            [3]  For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
            17.  Definitions                                      customers using or selling these products for use in such applications do so
                                                                          at their own risk and agree to fully indemnify Philips Semiconductors for any
                                                                          damages resulting from such application.
            Short-form specification —The data in a short-form specification is         Right to make changes —Philips Semiconductors reserves the right to
            extracted from a full data sheet with the same type number and title. For        make changes in the products - including circuits, standard cells, and/or
            detailed information see the relevant data sheet or data handbook.            software - described or contained herein in order to improve design and/or
            Limiting values definition — Limiting values given are in accordance with     performance. When the product is in full production (status ‘Production’),
            the Absolute Maximum Rating System (IEC60134). Stress above one or       relevant changes will be communicated via a Customer Product/Process
            more of the limiting values may cause permanent damage to the device.        Change Notification (CPCN). Philips Semiconductors assumes no
            These are stress ratings only and operation of the device at these or at any      responsibility or liability for the use of any of these products, conveys no
            other conditions above those given in the Characteristics sections of the        license or title under any patent, copyright, or mask work right to these
            specification is not implied. Exposure to limiting values for extended periods     products,andmakesnorepresentationsorwarrantiesthattheseproductsare
            may affect device reliability.                                          freefrompatent,copyright,ormaskworkrightinfringement,unlessotherwise
                                                                          specified.
            Application information — Applications that are described herein for any
            of these products are for illustrative purposes only. Philips Semiconductors
            makenorepresentationorwarrantythatsuchapplicationswillbesuitablefor    19.  Trademarks
            the specified use without further testing or modification.
            18.  Disclaimers                                     Notice —All referenced brands, product names, service names and
                                                                          trademarks are the property of their respective owners.
            Life support —These products are not designed for use in life support
            appliances, devices, or systems where malfunction of these products can
            reasonably be expected to result in personal injury. Philips Semiconductors
            20.  Contact information
            For additional information, please visit:  http://www.semiconductors.philips.com
            For sales office addresses, send an email to:  sales.addresses@www.semiconductors.philips.com
            74HC_HCT4040_3                                                                            ©KoninklijkePhilipsElectronicsN.V.2005.Allrightsreserved.
            Product data sheet                             Rev. 03 — 14 September 2005                                       23 of 24

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第24頁:
                                                                                74HC4040;  74HCT4040
            Philips Semiconductors
                                                                                                  12-stage binary ripple counter
            21.  Contents
            1       General description. . . . . . . . . . . . . . . . . . . . . .  1
            2       Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  1
            3       Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . .  1
            4       Quick reference data. . . . . . . . . . . . . . . . . . . . .  1
            5       Ordering information. . . . . . . . . . . . . . . . . . . . .  2
            6       Functional diagram . . . . . . . . . . . . . . . . . . . . . .  3
            7       Pinning information. . . . . . . . . . . . . . . . . . . . . .  4
            7.1       Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  4
            7.2       Pin description . . . . . . . . . . . . . . . . . . . . . . . . .  5
            8       Functional description  . . . . . . . . . . . . . . . . . . .  5
            8.1       Function table. . . . . . . . . . . . . . . . . . . . . . . . . .  5
            8.2       Timing diagram. . . . . . . . . . . . . . . . . . . . . . . . .  6
            9       Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . .  6
            10     Recommended operating conditions. . . . . . . .  7
            11     Static characteristics. . . . . . . . . . . . . . . . . . . . .  7
            12     Dynamic characteristics . . . . . . . . . . . . . . . . .  11
            13     Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . .  15
            14     Package outline . . . . . . . . . . . . . . . . . . . . . . . .  17
            15     Revision history. . . . . . . . . . . . . . . . . . . . . . . .  22
            16     Data sheet status. . . . . . . . . . . . . . . . . . . . . . .  23
            17     Definitions  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  23
            18     Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . .  23
            19     Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .  23
            20     Contact information  . . . . . . . . . . . . . . . . . . . .  23
                                                                          © Koninklijke Philips Electronics N.V.  2005
                                                                          Allrightsarereserved.Reproductioninwholeorinpartisprohibitedwithouttheprior
                                                                          writtenconsentofthecopyrightowner.Theinformationpresentedinthisdocumentdoes
                                                                          notformpartofanyquotationorcontract,isbelievedtobeaccurateandreliableandmay
                                                                          be changed without notice. No liability will be accepted by the publisher for any
                                                                          consequenceofitsuse.Publicationthereofdoesnotconveynorimplyanylicenseunder
                                                                          patent- or other industrial or intellectual property rights.
                                                                                                            Date of release: 14 September 2005
                                                                                                          Document number: 74HC_HCT4040_3
                                                                          Published in The Netherlands

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